Single crystal wafer and solar battery cell

ABSTRACT

The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of α (0°&lt;α&lt;90°) for the [011] direction, β (0°&lt;β&lt;90°) for the [01-1] direction and γ (0°≦γ&lt;45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.

TECHNICAL FIELD

The present invention relates to a single crystal wafer used for deviceproduction processes, which can have a smaller thickness compared withconventional wafers, a MIS type semiconductor device and solar cellutilizing the wafer.

BACKGROUND ART

Single crystal wafers, of which typical examples are those of silicon(Si) and gallium arsenide (GaAs), are obtained by slicing a singlecrystal ingot produced by the Czochralski method (CZ method) or thefloating zone method (FZ method) into wafers. Therefore, it is desiredto obtain wafers as many as possible from one ingot by making thicknessof wafer as small as possible or reducing the stock removal for slicing.That is, desirability of reducing thickness of wafers or processing lossin the production of wafers to reduce waste of the raw material andthereby reduce production cost of wafers has hitherto been widelyrecognized.

However, if thickness of wafer is simply reduced, it becomes likely thatbreakage or chipping occurs in the wafer production process or deviceproduction process. Therefore, it is considered that wafers must have acertain thickness (for example, about 700 to 800 μm in the case of asilicon wafer having a diameter of 200 mm). Further, since a limitationis imposed on the reduction of stock removal for slicing by slicingapparatus, the reduction of stock removal for slicing suffers from acertain limit.

Furthermore, loss of the raw material is generated not only in the waferproduction process, but also in the device production process. Since thefinal thickness of wafer actually mounted as a chip is about 100 to 200μm, a step of reducing the thickness from the back surface (back lap) isused, and thus the raw material is wasted also in this step.

Meanwhile, a gate insulator film of MIS (metal/insulator film/silicon)type transistor mainly produced by using a silicon single crystal waferis required to have highly efficient electric characteristics and highreliability such as low leakage current characteristic, low interfacestate density and high carrier injection resistance. As a technique forforming a gate insulator film satisfying these requirements, there hasconventionally been utilized the thermal oxidation technique usingoxygen molecules or water molecules at 800° C. or higher.Conventionally, in order to obtain good oxide film/silicon interfacecharacteristics, oxide dielectric breakdown voltage characteristic andleakage current characteristic by using the thermal oxidation technique,there must be used a silicon wafer having a {100} plane for the surfaceor a silicon wafer having a plane orientation tilting by about 4° from a{100} plane of a single crystal.

If a gate oxide film is formed on a silicon wafer having a planeorientation other than those mentioned above by using the thermaloxidation technique, electric characteristics are degraded, that is, theinterface state density of oxide film/silicon interface becomes high,the oxide dielectric breakdown voltage characteristic and leakagecurrent characteristic are degraded and so forth. Therefore, as asilicon wafer on which semiconductor devices such as MIS typetransistors are formed, a silicon wafer having a {100} plane for thesurface or a silicon wafer having a plane orientation tilting by about4° from a {100} plane of a single crystal has conventionally been used.

However, in a silicon wafer having a {100} plane for the surface, a{110} plane serving as a cleavage plane exists perpendicularly to thesurface. Thus, breakages, chipping, slip dislocations and so forth arelikely to be caused during the process. Therefore, a usually usedsilicon wafer having a {100} plane for the surface has a thickness ofabout 700 to 800 μm for a diameter of 200 mm or a thickness of about 600to 700 μm for a diameter of 150 mm, and the same shall apply to asilicon wafer having a plane orientation tilting by about 4° from a{100} plane of a single crystal.

Recently, a technique was developed for forming an insulator film ofgood quality irrespective of the plane orientation of silicon wafersurface (refer to 2000 Symposium ON VLSI Technology, Honolulu, Hi., Jun.13-15, 2000 “Advantage of Radical Oxidation for Improving Reliability ofUltra-Thin Gate Oxide”). Therefore, it can be said that, thanks to sucha technique, it became unnecessary to limit the plane orientation ofwafer for the production of MIS type semiconductor devices to the {100}surface.

DISCLOSURE OF THE INVENTION

Therefore, to effectively utilize the aforementioned technique offorming an insulator film of good quality irrespective of the planeorientation, an object of the present invention is to provide a singlecrystal wafer that can bear the device production process to a degreecomparable to those attained conventional wafers even with a smallerthickness of the water compared with those of the conventional wafers onthe basis of relationship between plane orientation and likeliness ofbreakage, and thereby reduce loss of single crystal. Another object ofthe present invention is to provide an MIS type semiconductor device ora solar cell, of which major problem is reduction of production cost, ata low cost by utilizing a silicon wafer having such a plane orientationunlikely to cause breakage.

The present invention that achieves the aforementioned objects providesa single crystal wafer, wherein the main surface has a plane or a planeequivalent to a plane tilting with respect to a [100] axis of singlecrystal by angles of α (0°<α<90°) for the [011] direction, β (0°<β<90°)for the [01-1] direction and γ (0°≦γ<45°) for the [10-1] or [101]direction.

Since the surface of such a single crystal wafer has a plane orientationtilting with respect to all the {110} planes, at which cleavage islikely to occur, it becomes more unlikely to suffer from breakage due toan external stress compared with a conventional single crystal waferhaving a {100} plane. Thus, wafers having a thickness smaller than thoseof conventional wafers can be produced. Therefore, number of wafers thatcan be produced from one single crystal ingot is increased, and itbecomes possible to reduce the cost.

The single crystal wafer of the present invention may consist ofsemiconductor silicon.

If the single crystal wafer consists of semiconductor silicon asdescribed above, the effect of the reduction of production cost becomeextremely significant, since semiconductor silicon is the most widelyused semiconductor at present.

The aforementioned single crystal wafer may satisfy a relationship ofthickness of wafer (μm)/diameter of wafer (mm) ≦3.

Since the single crystal wafer of the present invention can haveexcellent mechanical strength as described above, it can be such anwafer having an extremely thin wafer thickness relative to diameter ofthe wafer that it should satisfy the relationship of thickness of wafer(μm)/diameter of wafer (mm) ≦3, which cannot be realized by theconventional techniques. Therefore, the effect provided by the reductionof production cost becomes more significant.

In the single crystal wafer of the present invention, an insulator filmis preferably formed on the surface of the single crystal wafer.

If an insulator film is formed on at least one surface of the singlecrystal wafer of the present invention as described above, cleavage ofthe wafer can be suppressed. If the insulator film is formed all overthe wafer, the effect of suppressing the cleavage becomes moresignificant. Further, MIS semiconductor devices, for example, can beproduced by using such a wafer, and thus the devices can be produced ona thin wafer that is unlikely to break at a low cost.

In this case, the aforementioned insulator film is preferably a siliconoxide film containing Kr, or the aforementioned insulator film ispreferably a silicon nitride film containing Ar or Kr and hydrogen.

If the insulator film is a silicon oxide film containing Kr or a siliconnitride film containing Ar or Kr and hydrogen as described above, aninsulator film of good quality can be obtained irrespective of the planeorientation.

Furthermore, a solar cell can be produced by using the single crystalwafer of the present invention described above.

Solar cells have not used so widely because of the high production costthereof. Therefore, if the wafer of the present invention that hashigher strength and enables processing of thin silicon single crystal isused, the production cost of solar cells can be reduced and it providesgreat advantages.

As described above, the single crystal wafer of the present inventioncan be a single crystal wafer that can bear the device productionprocess to a degree comparable to those attained by conventional waferseven with a smaller thickness of the water compared with those of theconventional wafers. Therefore, loss of the single crystal raw materialcan be markedly reduced compared with conventional techniques, and byusing such a silicon wafer, an MIS type semiconductor device or a solarcell, of which major problem is reduction of production cost, can beprovided at a low cost.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is an explanatory diagram for explaining plane orientation of thesingle crystal wafer of the present invention.

FIG. 2 shows an exemplary apparatus utilizing a radial line slot antennafor forming an oxide film on the single crystal wafer of the presentinvention.

FIG. 3 is a graph showing a relationship between oxide film thicknesscontaining Kr and oxidation time during oxidation of silicon wafersurface using Kr/O₂ high density plasma.

FIG. 4 is a graph showing the results of low frequency C-V measurementfor interface state density of oxide film.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereafter, the present invention will be explained in more detail.

As described above, in response to the development of a technique forforming an insulator film of good quality irrespective of the planeorientation of silicon wafer surface, the inventors of the presentinvention noted the relationship between the plane orientation andlikeliness of breakage of wafer in order to utilize the technique. Thatis, since it became unnecessary to limit the plane orientation for thedevice characteristics, they conceived that, if a plane orientationproviding strength as high as possible was selected, wafers causingbreakage or chipping at a level comparable to those attained byconventional wafers could be obtained even if the wafers were producedwith a smaller thickness compared with those of the conventional wafers,and as a result, number of wafers obtainable from one ingot could beincreased.

Meanwhile, as for the plane orientation of silicon wafers on whichdevices are produced, while low index planes such as {100} plane and{111} plane have been used from old days, wafers having a planeorientation tilting from such plane orientation have also been used. Forexample, the inventions disclosed in Japanese Patent Laid-openPublication (Kokai) No. 56-109896, Japanese Patent Publication (Kokoku)No. 3-61634 and Japanese Patent Laid-open Publication No. 8-26891 useplanes tilting from a {100} plane or {111} plane by several degrees forone {110} plane. However, these planes tilt for only one {110} plane,and the wafers cannot be said to be wafers that are unlikely to break.Moreover, those techniques relate to prevention of generation ofprocess-induced crystal defects or prevention of generation of defectsduring epitaxial growth.

Further, Japanese Patent Laid-open Publication No. 9-262825 disclosesthat, as for the relationship between the plane orientation andlikeliness of breakage of wafer, when a single crystal is sliced with awire saw, wafers are likely to suffer from breakage if a saw markconforms to the cleavage direction. However, the cleavage planeconsidered in this reference is only the {110} plane orthogonal to the{100} plane, and the {110} plane having an angle of 45° with respect tothe {100} plane is not considered at all. Thus, all the sliced wafersare wafers having a low index plane such as {100} plane.

The inventors of the present invention conceived that, in order toproduce a wafer unlikely to break, consideration of only the {110} planeperpendicular to the {100} plane was insufficient, and it was necessaryto consider the {110} plane having an angle of 45° with respect to the{100} plane. Thus, the present invention was accomplished.

Hereafter, the present invention will be explained by referring to theappended drawings. However, the present invention is not limited tothese explanations.

FIG. 1 is a diagram for explaining plane orientation of the singlecrystal wafer of the present invention. The arrowhead (vector)represented by the bold line in FIG. 1 indicates the plane orientationof the single crystal wafer of the present invention (orientation of thenormal of the wafer surface). It has, with respect to the [100] axis(X-axis), tilting angles of α (0°<α<90°) for the [011] direction, β(0°<β<90°) for the [01-1] direction and γ (0°≦γ<45°) for the [10-1]direction.

That is, the single crystal wafer having this plane orientation willhave a plane tilting by angles of α, β and γ from the cleavage planes,(011) plane, (01-1) plane and (10-1) plane, respectively, and thusmechanical strength of the wafer with respect to an external stress isincreased compared with conventional wafers having a low index planeorientation.

In this case, if α=β, γ becomes 0°. If a cross section of a wafer havingsuch a tilting plane is observed from the [010] direction, the cleavageplanes, the (10-1) plane and (101) plane, are bilaterally symmetricalplanes having an angle of 45° with respect to the (100) plane,respectively. Therefore, if the number of effective bonds of the crystaldoes not show significant difference for all of the plane orientations,it is considered that the strength becomes highest when γ=0°. However,it is considered that actual strength is determined by both of the planeorientation and number of effective bonds, and thus γ of 0° cannot besaid to be always optimal since the number of effective bonds differsdepending on the plane orientation. Therefore, even when γ satisfies thecondition of 0°<γ<45°, high strength can be obtained. Incidentally, itis known that the numbers of effective bonds in the case of siliconsingle crystal are 11.8 ×10¹⁴ numbers/cm², 9.6 ×10¹⁴ numbers/cm² and 6.8×10¹⁴ numbers/cm² for the (111), (110) and (100) planes, respectively.

Further, when α<β, γdoes not mean an tilting angle for the [10-1]direction shown in FIG. 1, but means a tilting angle for the [101]direction.

In addition, as a plane orientation equivalent to that of the singlecrystal wafer shown in FIG. 1, there are three planes in the directionscorresponding to those obtained by revolving the vector shown in FIG. 1by 90° at a time on the y-z plane.

In order to produce a wafer having such a particular tilting plane, asingle crystal ingot produced under ordinary condition can be slicedwith a predetermined angle. In the case of silicon single crystal,ingots ordinarily produced have a crystal orientation of <100> or <111>,and <110> and <511> are known as crystal orientations that enablecrystal production without causing unacceptable deformation of crystal.Further, by using a seed crystal preliminarily provided with an offangle of several degrees or so as a seed crystal used at the time ofpulling a single crystal, a crystal having an off angle can be pulled.Therefore, by using such a crystal, adjustment of the orientation at thetime of slicing can also be simplified.

Since the surface of the single crystal wafer of the present inventiondescribed above has a plane orientation tilting from all of the {110}planes along which cleavage is likely to occur, a wafer that is moreunlikely to break with an external stress and has a smaller thicknesscompared with conventional wafers having {100} planes can be produced.

For example, when a single crystal wafer is produced from semiconductorsilicon, it is necessary to produce a wafer having a thickness of about700 to 800 μm in the case of a conventional silicon wafer having adiameter of 200 mm. However, in the single crystal wafer of the presentinvention, the thickness can be made thinner than the above, and it isalso possible to obtain a thickness of less than 600 μm in the case of asilicon wafer having a diameter of 200 mm, for example. Therefore,number of wafers that can be produced from one single crystal ingot isincreased, and it becomes possible to reduce the production cost.

Hereafter, the method for forming a gate insulator film required for MIStype semiconductor devices by using a silicon wafer having such atilting plane (referred to as “(abc) plane” hereinafter) will beexplained.

If an insulator film is formed by the method described below, aninsulator film having characteristics as a gate insulator filmcomparable to those of conventional films and showing no dependency onthe plane orientation can surely be formed.

FIG. 2 shows an exemplary apparatus utilizing a radial line slot antennafor forming an oxide film on the single crystal wafer of the presentinvention. This embodiment has a novel characteristic that Kr is used asplasma excitation gas for the oxide film formation. Inside of a vacuumchamber (processing chamber) 1 is made vacuum, and Kr gas and O₂ gas areintroduced from a shower plate 2 to adjust the pressure in theprocessing chamber to be about 1 Torr (about 133 Pa).

A circular substrate 3 such as a silicon wafer is placed on a samplestand 4 having a heating mechanism, and temperature is adjusted so thatthe temperature of the sample should become 400° C. This temperature maybe in the range of 200 to 550° C. From a coaxial wave guide 5, amicrowave of 2.45 GHz is supplied to the processing chamber via a radialline slot antenna 6 and a dielectric plate 7 to generate high densityplasma in the processing chamber. Further, any frequency of the suppliedmicrowave may be selected so long as it is in the range of 900 MHz to 10GHz.

A spacing between the shower plate 2 and the substrate 3 is adjusted to6 cm in this embodiment. A narrower spacing enables film formation witha higher rate. Although an example of film formation using a plasmaapparatus utilizing a radial line slot antenna was shown in thisembodiment, a microwave may be introduced into the processing chamber byusing another method.

In the high density excitation plasma in which Kr gas and O₂ gas aremixed, Kr* and O₂ molecules in an intermediate excited state collideeach other, and thus atomic oxygen O* generates efficiently. Thesubstrate surface is oxidized with this atomic oxygen. The conventionaloxidation of silicon surface is attained by H₂O molecules and/or O₂molecules, and the treatment temperature is extremely high, i.e., 800°C. or higher. However, the oxidation by atomic oxygen according to thepresent invention may be realized at a sufficiently low temperature,i.e., 550° C. or lower.

Although higher pressure in the processing chamber is desirable forincreasing occasions of collision of Kr* and O₂, O* will collide eachother and return into a O₂ molecule at an unduly high pressure. Theinventors of the present invention measured thickness of oxide filmgrown by oxidation treatment of 10 minutes at a silicon substratetemperature of 400° C. with keeping pressure ratios of 97% for Kr and 3%for oxygen in the processing chamber and a varying gas pressure in theprocessing chamber. As a result, the thickness of oxide film became thelargest when the gas pressure in the processing chamber was 1 Torr, andthus it was found that oxidation condition of that pressure or pressurearound that was preferred. It was found that this pressure condition wassimilarly preferred for the (abc) plane as well as the (100) plane andthe (111) plane.

FIG. 3 shows a relationship between oxide film thickness containing Krand oxidation time during oxidation of silicon wafer surface using Kr/O₂high density plasma. The graph shows the results for silicon substrateshaving a plane orientation of (100) plane, (111) plane or (abc) plane.FIG. 3 also shows oxidation time dependency in conventional dry thermaloxidation at 900° C. It is evident that the oxidation rate in the Kr/O₂high density plasma oxidation at a substrate temperature of 400° C. anda processing chamber pressure of 1 Torr is higher than the oxidationrate in the dry O₂ oxidation at a substrate temperature of 900° C. andatmospheric pressure.

By using the silicon substrate surface oxidation with Kr/O₂ high densityplasma, the productivity of surface oxidation technique can also bemarkedly improved. In the conventional high temperature oxidationtechnique, O₂ molecules or H₂O molecules pass through an oxide filmformed on a surface by diffusion and reach the interface ofsilicon/silicon oxide film to contribute to the oxidation. Therefore, itis a common knowledge that the oxidation rate is rate-determined by thediffusion rates of O₂ molecules or H₂O molecules through the oxide film,and it increases with a factor of t^(1/2) as a function of oxidationtime t. However, in the Kr/O₂ high density plasma oxidation according tothe present invention, the oxidation rate is linear until the oxide filmthickness reaches 35 nm. This means that the diffusion rate of atomicoxygen in the silicon oxide film is extremely high, and atomic oxygencan freely pass through the silicon oxide film.

Kr density distribution along the depth direction in a silicon oxidefilm formed by the aforementioned procedure was investigated by using atotal reflection X-ray fluorescence spectrophotometer. Kr densitydecreased in a region having a thinner oxide film thickness, and Krexisted at a density of about 2×10¹¹ cm⁻² at a silicon oxide filmsurface. That is, in this silicon film, the Kr concentration in the filmis constant for the film thickness of 4 nm or more, and the Krconcentration decreases towards the silicon/silicon oxide filminterface.

FIG. 4 shows the results of low frequency C-V measurement for interfacestate density of an oxide film. The silicon oxide film was formed at asubstrate temperature of 400° C. by using the apparatus shown in FIG. 2.The partial pressure of oxygen in rare gas was fixed to 3%, and thepressure in the processing chamber was fixed to 1 Torr. For comparison,the interface state density of a thermal oxide film formed at 900° C. inan atmosphere of 100% oxygen is also shown. The interface state densityof the oxide film formed by using Kr gas was low for all of the (100)plane, (111) plane and (abc) plane and equivalent to the interface statedensity of the thermal oxide film formed at 900° C. in a dry oxidationatmosphere so as to have a (100) plane. Thus, it can be seen that anoxide film of good quality showing a low interface state density cansimilarly be obtained for the (abc) plane. In addition, the interfacestate density of the thermal oxide film formed with the (111) plane islarger by 1 digit order compared with them. The interface state densityreferred to in the present invention means interface trap density (Dit)in the mid gap, and it is obtained by the quasi-static C-V technique(quasi-static capacitance-voltage technique).

As for electric characteristics and reliability characteristics of theoxide film such as dielectric breakdown voltage, leakage characteristic,hot carrier resistance and charge quantity causing breakdown of siliconoxide film upon flowing a stress current, QBD (Charge-to-Breakdown), theoxide film obtained by the silicon substrate surface oxidation usingKr/O₂ high density plasma showed favorable characteristics comparable tothose obtained for the oxide film obtained by the thermal oxidation at900° C.

As described above, although the oxide film grown with the Kr/O₂ highdensity plasma was oxidized at a low temperature of 400° C., it showedcharacteristics comparable to or superior to those shown by theconventional oxide film of a (100) plane obtained by the hightemperature thermal oxidation, even for the (abc) plane, without beinginfluenced by the plane orientation. These advantages are partlyprovided by Kr contained in the oxide film. It is considered that whenKr is contained in the oxide film, stress in the film or at the Si/SiO₂interface is relaxed, charges in the film and the interface statedensity are reduced, and thereby the electric characteristics of thesilicon oxide film are markedly improved. It is considered that, inparticular, Kr contained at a level of 5×10¹¹ cm⁻² or less in theconcentration of the surface contributes to the improvements of theelectric characteristics and reliability characteristics of the siliconoxide film.

The MIS transistor utilizing this gate oxide film shows favorablecharacteristics in any plane orientation, and characteristics equivalentto those obtained with the (100) plane can be obtained even with the(abc) plane.

In addition, in order to produce the oxide film of the presentinvention, other than the apparatus shown in FIG. 2, an apparatus forplasma process that enables low temperature oxide film formation usingplasma may also be used.

For example, an oxide film can also be formed by a two-stage showerplate type plasma process apparatus having first gas discharging meansfor discharging Kr gas for exciting plasma by a microwave and second gasdischarging means for discharging oxygen gas, which is different fromthe first gas discharging means.

Hereafter, low temperature nitride film formation using plasma will beexplained. A nitride film forming apparatus is almost the same as theapparatus shown in FIG. 2. In this embodiment, Ar or Kr is used asplasma excitation gas for the nitride film formation. Inside of thevacuum chamber (processing chamber) 1 is made vacuum, and Ar gas and NH₃gas are introduced from the shower plate 2 to adjust the pressure in theprocessing chamber to be about 100 mTorr. A circular substrate 3 such asa silicon wafer is placed on the sample stand 4 having a heatingmechanism, and temperature is adjusted so that the temperature of thesample should become 500° C. This temperature may be adjusted to be inthe range of about 200 to 550° C.

From the coaxial wave guide 5, a microwave of 2.45 GHz is supplied tothe processing chamber via the radial line slot antenna 6 and thedielectric plate 7 to generate high density plasma in the processingchamber. The frequency of the supplied microwave may be in the range of900 MHz to 10 GHz. A spacing between the shower plate 2 and thesubstrate 3 is adjusted to 6 cm in this example. A narrower spacingenables film formation with a higher rate.

Although an example of film formation using a plasma apparatus utilizinga radial line slot antenna was shown in this embodiment, a microwave maybe introduced into the processing chamber by using another method.Further, although Ar is used as the plasma excitation gas, use of Kr canalso provide similar results. Furthermore, although NH₃ is used as theplasma process gas, a mixed gas of N₂ and H₂ or the like may also beused.

In the high density excitation plasma of a mixed gas of Ar or Kr and NH₃(or N₂, H₂), NH* radicals are efficiently generated by Ar* or Kr* in anintermediate excited state. With these NH* radicals, the substratesurface is nitrided. Such nitriding of silicon enables formation ofnitride film of high quality at a low temperature without limitation ofthe plane orientation of silicon.

In the silicon nitride film formation according to the presentinvention, one of the important requirements is the presence ofhydrogen. When hydrogen exists in the plasma, dangling bonds in thesilicon nitride film or at the interface form Si—H and N—H bonds tocause termination, and as a result, electronic traps in the siliconnitride film and at the interface are eliminated. The presence of theSi—H bonds and N—H bonds in the nitride film of the present inventionhas been confirmed by infrared absorption spectrometry and X-rayphotoelectron spectrometry of the film. The presence of hydrogen alsoeliminates the hysteresis of CV characteristics and suppresses thesilicon/silicon nitride interface state density as low as 3 ×10¹⁰ eV⁻¹cm⁻². In the formation of the silicon nitride film by using a rare gas(Ar or Kr) and a mixed gas of N₂/H₂, if the hydrogen gas is used at apartial pressure of 0.5% or more, electron and hole traps in the filmare sharply decreased.

Relative dielectric constant of the silicon nitride film of thisembodiment was 7.9, which is twice as large as that of the silicon oxidefilm.

In order to produce the nitride film of the present invention, otherthan the apparatus shown in FIG. 2, an apparatus for plasma process thatenables low temperature nitride film formation using plasma may also beused. For example, the nitride film can also be formed by a two-stageshower plate type plasma process apparatus having first gas dischargingmeans for discharging Ar or Kr gas for exciting plasma by a microwaveand second gas discharging means for discharging NH₃ (or N₂/H₂ gas) gas,which is different from the first gas discharging means.

Hereafter, a method for producing a solar cell by using a silicon waferhaving an (abc) plane such as the wafer of the present invention will beexplained.

As already described, a silicon wafer having an (abc) plane as the mainsurface shows high mechanical strength. Therefore, it becomes possibleto slice a silicon single crystal ingot for solar cells with a thicknesssmaller than the thickness used in the slicing of conventional siliconsingle crystal ingot for solar cells (about 400 to 600 μm for a diameterof 100 to 150 mm), and the thickness can be, for example, 300 to 450 μmor less than the foregoing range for a diameter of 100 to 150 mm.Therefore, the yield of wafers is improved for the thickness madethinner, and thus it becomes possible to reduce the cost.

The slicing is performed by using a wire saw or an inner diameterslicer, and damage is generated in a crystal by mechanical impact at thetime of the slicing. Such damage degrades electric characteristics ofwafers and also affect characteristic of the cell. Therefore, in orderto eliminate such a damage layer, chemical etching is performed forabout 10 to 20 μm. Such etching is usually performed by using a mixedacid of HF and HNO₃, and several tens of wafers are put into a carrierfor etching to perform the etching with rotating the carrier in order toattain uniform etching over the surfaces. Therefore, higher waferstrength is advantageous for such an etching process, since wafers areunlikely to break even with a small thickness. Further, etching with analkali for increasing conversion efficiency, called texture treatment,is also performed.

Then, since a p-type silicon wafer is usually used, n-type impuritiesare diffused in the wafer to form a pn junction, and the wafer issubjected to formation of electrodes and formation of antireflectionfilm to produce a solar cell.

By successively forming a n-type layer, p-type layer and n-type layer ona surface of a p-type wafer by epitaxial growth to produce a pnpn typetandem structure, a conversion efficiency of 20% or more and an outputvoltage of 1.5 V can be attained.

As described above, the wafer of the present invention having the (abc)plane as the main surface can sufficiently bear the production steps ofdevices and solar cells even with a smaller thickness, and thus itenables marked reduction of the production cost.

The present invention is not limited to the embodiments described above.The above-described embodiments are mere examples, and those having thesubstantially same structure as that described in the appended claimsand those providing similar functions and advantages are all included inthe scope of the present invention.

For example, while single crystal wafers consisting of semiconductorsilicon are exemplified in the aforementioned embodiments, the presentinvention is not limited to these and can be applied to single crystalsother than silicon and compound semiconductors, and such applicationalso falls within the scope of the present invention.

1. A semiconductor silicon single crystal wafer, wherein the mainsurface of the semiconductor silicon single crystal wafer has a plane ora plane equivalent to a plane tilting with respect to a [100] axis ofsingle crystal by angles of α (0°<α<90°) for the [011] direction, β(0°<β<90°) for the [01-1] direction and γ (0°<γ<45°) for the [10-1] or[101] direction, the diameter of the wafer is not less than 100 mm andnot more than 200 mm, and the wafer satisfies a relationship of 2≦thickness of wafer (μm)/diameter of wafer (mm) ≦3.
 2. A single crystalwafer, wherein an insulator film is formed on a surface of the singlecrystal wafer according to claim
 1. 3. The single crystal waferaccording to claim 2, wherein the insulator film is a silicon oxide filmcontaining Kr.
 4. A solar cell produced by using the single crystalwafer according to claim
 3. 5. The single crystal wafer according toclaim 2, wherein the insulator film is a silicon nitride film containingAr or Kr and hydrogen.
 6. A solar cell produced by using the singlecrystal wafer according to claim
 5. 7. A solar cell produced by usingthe single crystal wafer according to claim
 2. 8. A solar cell producedby using the single crystal wafer according to claim 1.